There are many state machines which are used in logical circuits. Among them, there is one which is often used with more or less improvements in the basic circuit in order to adapt said state machine to the purposes that it is supposed be used.
FIG. 1 shows the implementation of a general Moore state machine. It comprises a combinational circuit (1) which receives a set of input signals (3) (X1, . . . , Xm) and which generates a set of data signals (D1, . . . , D4) to a state variable register (2) (or latches). This state variable (2) is clocked by a clock signal (7) and generates the output signals (5) (Q1, . . . , Q4) to the output decode (9). Those output signals (5) also loop back to the combinational circuit (1) in order to indicate the current state of the state machine. According to those signals Q(t) the output decode (9) generates a plurality of output signals (Z1, Z2, . . . , Zn) which will then be used by the downward circuit. The output decode (9) is separated from the combinational circuit (1) and the register (2) because the outputs set (Z1, . . . , Zn) depends only on the state machine set of inputs (X1, . . . , Xm). The resulting outputs do not appear until the clock pulse (7) causes the flip-flops to change state.
The general model for the clocked Moore state machine is often used because it is fully adapted to a memory interface design and has a reliable structure. But the state duration of the Moore state machine is not programmable and the minimum value is one clock cycle.